1. Technical Field
The present invention generally relates to a multi-chip device and a method for manufacturing the same, and more specifically, to a technology of transmitting a signal through light with an LED (Light Emitting Diode) element and an LED sensor to reduce design and manufacturing cost.
2. Description of the Related Art
A circuit generally includes several chips bonded together with connections provided therebetween. The chips may be bonded by a flip chip process or by a wire bonding process. However, with the wire bonding process, a length of the wire connecting the chips reaches several millimeters, resulting in significant signal delays. As a result, the number of chips that can be bonded together is limited.
Recently, a technology of forming through-hole electrodes through a chip to provide a signal transmission path has been developed. Particularly, after a circuit is formed on a wafer, the wafer is polished to less than 100 μm, and through-holes are formed through the wafer and then coated with metal to form connection electrodes. Thousands of through-hole electrodes may be formed in one chip in this manner, and several chips may be interconnected in a single package.
After chips are formed with the through-hole electrodes, the chips can be connected at certain points with the shortest path. Therefore, the through-hole electrodes through the chips have eliminated the limit of the number of chips that can be bonded together through wire bonding.
Alternative methods for forming connections between a plurality of chips have been developed. For example, when a plurality of chips include small-sized inductors and capacitors for providing transmission through electromagnetic or electrostatic coupling, wireless coupling between the chips may be a substitute for wire bonding or through-hole electrodes.
Techniques for forming circuits in semiconductor chips are key to high performance, low power consumption, and low cost of the circuits. When features of the elements in the circuits become miniaturized, a line delay increases as a result of increased parasitic capacitance, thereby affecting the performance of the circuits. The increase of line delay time may be reduced by using materials having a small dielectric constant as interlayer insulating films or inserting a repeater into a path. However, the repeater increases leakage current and power consumption of the chip.